An efficient FPGA implementation of the Advanced
Encryption Standard algorithm
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For a long time, the Data Encryption Standard (DES) was
considered as a standard for the symmetric key encryption.
DES has a key length of 56 bits. However, this key length is
currently considered small and can easily be broken. For this
reason, the National Institute of Standards and Technology
(NIST) opened a formal call for algorithms in September 1997.
A group of fifteen AES candidate algorithms were announced
in August 1998. Next, all algorithms were subject to
assessment process performed by various groups of
cryptographic researchers all over the world. In August 2000,
NIST selected five algorithms: Mars, RC6, Rijndael, Serpent
and Twofish as the final competitors. These algorithms were
subject to further analysis prior to the selection of the best
algorithm for the AES. Finally, on October 2, 2000, NIST
announced that the Rijndael algorithm was the winner.
Rijndael can be specified with key and block sizes in any
multiple of 32 bits, with a minimum of 128 bits and a
maximum of 256 bits. Therefore, the problem of breaking the
key becomes more difficult . In cryptography, the AES is
also known as Rijndael . AES has a fixed block size of 128
bits and a key size of 128, 192 or 256 bits.
The AES algorithm can be efficiently implemented by
hardware and software. Software implementations cost the
smallest resources, but they offer a limited physical security
and the slowest process. Besides, growing requirements for
high speed, high volume secure communications combined
with physical security, hardware implementation of
cryptography takes place.
An FPGA implementation is an intermediate solution
between general purpose processors (GPPs) and application
specific integrated circuits (ASICs). It has advantages over
both GPPs and ASICs. It provides a faster hardware solution
than a GPP. Also, it has a wider applicability than ASICs since
its configuring software makes use of the broad range of
functionality supported by the reconfigurable device .
This paper deals with an FPGA implementation of an AES
encryptor/decryptor using an iterative looping approach with
block and key size of 128 bits. Besides, our design uses the
lookup- table implementation of S-box. This method gives very
low complexity architecture and is easily operated to achieve
low latency as well as high throughput.
Organization of the rest of this paper is as follows. Section
2 provides a brief overview of AES algorithm. Design of AES
based on FPGA implementation is presented in section 3.
Section 4 gives simulation results followed by the comparisons
with other works in section 5. Finally, section 6 gives the
conclusion of this work.
DESCRIPTION OF AES ALGORITHM
The AES algorithm is a symmetric block cipher that can
encrypt and decrypt information. Encryption converts data to
an unintelligible form called cipher-text. Decryption of the
cipher-text converts the data back into its original form, which
is called plain-text.
A. AES encryption
The AES algorithm operates on a 128-bit block of data and
executed Nr - 1 loop times. A loop is called a round and the
number of iterations of a loop, Nr, can be 10, 12, or 14
depending on the key length. The key length is 128, 192 or 256
bits in length respectively. The first and last rounds differ from
other rounds in that there is an additional AddRoundKey
transformation at the beginning of the first round and no
MixCoulmns transformation is performed in the last round. In
this paper, we use the key length of 128 bits (AES-128) as a
model for general explanation. An outline of AES encryption is
given in Fig. 1.
The SubBytes transformation is a non-linear byte
substitution, operating on each of the state bytes independently.
The SubBytes transformation is done using a once-precalculated
substitution table called S-box. That S-box table
contains 256 numbers (from 0 to 255) and their corresponding
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resulting values. More details of the method of calculating the
S-box table refers to . In this design, we use a look-up table
as shown in Table I. This is a more efficient method than
directly implementing the multiplicative inverse operation
followed by affine transformation.
The Advanced Encryption Standard algorithm is a
symmetric block cipher that can process data blocks of 128 bits
through the use of cipher keys with lengths of 128, 192, and
256 bits. An efficient FPGA implementation of 128 bit block
and 128 bit key AES algorithm has been presented in this
paper. The design is implemented on Altera using APEX20KC
FPGA which is based on high performance architecture. The
proposed design is implemented based on the iterative
approach for cryptographic algorithms. Our architecture is
found to be better in terms of latency, throughput as well as
area. The design is tested with the sample vectors provided by
FIPS 197 . The algorithm achieves a low latency and the
throughput reaches the value of 1054Mbit/sec for encryption
and 615 Mbit/sec for decryption.