The Peripheral Component Interconnect (PCI) architecture has become the most common method used to extend PCs for add-on adapters over the years. Originally intended for personal computer systems, the PCI architecture has penetrated into virtually every computing platform category, including servers, storage, communications, and a wide range of embedded control applications. From its early incarnation as a 32-bit 33MHz interconnect, it has been expanded to offer higher speeds (currently in widespread use at 64-bit 133MHz, with faster versions on the way). Most importantly, each advancement in PCI bus speed and width provided backward software compatibility, allowing designers to leverage the broad code base. Compared to the progress made every year in other areas of computer technology such as processors and video cards, computer I/O system technology would seem to be standing still… in fact it is. Since the introduction of the original PCI bus back in the early 90's, very little has changed in the way that data is handled inside the computer. The PCI local bus is a high performance bus for interconnecting chips, expansion boards and processor/memory subsystems.
The PCI bus has served well for the last 10 years and it will play a major role in the next few years. However, today's and tomorrow's processors and I/O devices are demanding much higher I/O bandwidth than PCI 2.2 or PCI-X can deliver and it is time to engineer a new generation of PCI to serve as a standard I/O bus for future generation platforms. There have been several efforts to create higher bandwidth buses and this has resulted in the PC platform supporting a variety of application-specific buses alongside the PCI I/O expansion bus. Today's software applications are more demanding of the platform hardware, particularly the I/O subsystems. Streaming data from various video and audio sources are now commonplace on the desktop and mobile machines and there is no baseline support for this time-dependant data within the PCI 2.2 or PCI-X specifications. Applications such as video-on-demand and audio re-distribution are putting real-time constraints on servers too. Many communications applications and embedded-PC control systems also process data in real-time. Today's platforms, (Figure 1.1), must also deal with multiple concurrent transfers at ever-increasing data rates. 
Data needs to be "tagged" so that an I/O system can prioritize its flow throughout the platform, since all data cannot be treated equal in real time computing. High performance peripherals and adapters developed, demanded high speed data transfer and a third generation I/O bus had to be developed. As successful as the PCI architecture has become, there is a limit to what can be accomplished with a multi-drop, parallel shared bus interconnect technology.  Issues such as clock skew, high pin count, trace routing restrictions in printed circuit boards (PCB), bandwidth and latency requirements, physical scalability, and the need to support Quality of Service (QoS) within a system for a wide variety of applications lead to the definition of the PCI Express™ architecture.
PCI Express is the natural successor to PCI, and was developed to provide the advantages of a state-of-the-art, high-speed serial interconnect technology and packet based layered architecture, but maintain backward compatibility with the large PCI software infrastructure. The key goal was to provide an optimized and universal interconnect solution for a great variety of future platforms, including desktop, server, workstation, storage, communications and embedded systems.
Approved as a standard on April 17 2002, PCI-Express is intended to be an evolutionary upgrade to the existing PCI bus . It will maintain complete hardware and software compatibility with all recent PCI devices. It is expected that PCI will coexist in many platforms to support today's lower bandwidth applications until a compelling need, such as a new form factor, causes a full migration to a fully PCI Express based platform.