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Transaction-level power analysis of VLSI digital systems
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abstract
The increasing complexity of VLSI digital systems has dramatically supported system-level representations in
modeling and design activities. This evolution makes often necessary a compliant rearrangement of the
modalities followed in validation and analysis tasks, as in the case of power performances estimation.
Nowadays, transaction-level paradigms are having a wider and wider consideration in the research on
electronic system-level design techniques. With regard to the available modeling resources, the most
relevant framework is probably the transaction-level extension of the SystemC language (SystemC/TLM),
which therefore represents the best platform for defining transaction-level design techniques.
In this paper we present a macro-modeling power estimation methodology valid for SystemC/TLM
prototypes and of general applicability. The present discussion illustrates the implementation modalities of
the proposed approach, verifying its effectiveness through a comparison with RTL estimation techniques.
& 2015 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license


Introduction
Over the last decade, several researches have been conducted to
develop electronic system level (ESL) approaches in the modeling and
analysis of microelectronic digital systems. The main motivations
behind these researches come from the need of design techniques at
an abstraction level higher than register transfer level (RTL). In fact,
RTL techniques are becoming less and less suitable to face the
complexity reached by many microelectronic products, as in the case
of VLSI devices made up of million of gates. More precisely, the
evaluations conducted on RTL prototypes may be onerous in terms of
execution times and design efforts, because it is necessary to work
with rather detailed descriptions of the system architecture. This can
burden the design activities and make it difficult to meet strict timeto-market
constraints. On the other hand, ESL design techniques allow
to work on system prototypes derived from functional specifications,
without having to deal with specific implementation details. In this
way, there are more chances to take major decisions in the early
design phases and with limited efforts, thus to speed up the flow
towards the silicon implementation.
Transaction level modeling (TLM) has established itself as an effective
ESL paradigm, especially in the description of the communication
tasks between interacting modules. More precisely, when describing a
complex digital system composed by several interconnected modules,
a transaction-level representation allows a good separation between
communication and elaboration tasks. The channel access is typically
mediated by calls to interface functions capable to transport consistent

data amount; each module is independent from the others with
regard to interconnectivity [1]. The main benefits due to these features
consist in the use of system prototypes that can be defined and
simulated in reduced times. Moreover, the high interoperability of
transaction-level models facilitates the realization of complex system
architectures.
Nowadays, power performances are often a crucial constraint in
the design of VLSI digital systems, in consequence of the wide diffusion
of battery-supplied devices as well as the reliability issues due to
high clock frequencies. The estimation of power dissipation is by now
a primary design matter, providing useful indications in the analysis of
implementation options and low-power solutions. Power estimation
on RTL representations has been extensively studied, and a number of
effective and well-tested techniques is now available [2–9]. More
specifically, we can distinguish between cumulative and cycle-accurate
RTL approaches [2]. In the first case, the power estimation is
achieved by evaluating a power model at the end of a simulation
period, on the basis of average input statistics. On the other hand, a
cycle-accurate technique leads to evaluate the power model at every
time cycle, requiring as input data cycle-based quantities.
In the design of a complex VLSI system, the realistic application of
these estimation techniques is usually based on a modular approach.
More precisely, the power model definition does not concern the
system as a whole, but rather is carried out on basic modules that
cover specific tasks. The RTL representation of the whole system is
built through an aggregation of the RTL description of these modules;
these latter can be realized by the designer or also taken from a third
part library. In order to define the power model of a basic module, it is
often necessary a characterization procedure which provides precise
power consumption data from low-level power simulations [2]. For a
specific CMOS technology, such characterization may be carried out once and for all, and the results may be reused for several VLSI systems
based on that technology. Finally, once built the power models of
the basic modules, we can perform power estimations on the whole
system in its RTL representation.
RTL techniques are often capable to provide reliable power estimations,
which can be used to verify design constraints as well as
evaluate different implementation options. However, for the reasons
before mentioned, many research interests are becoming more oriented
towards analysis techniques at electronic system level. In particular,
power estimations on transaction-level representations constitute
an attractive investigation field that needs to be explored more
deeply. In concrete terms, this means defining general and effective
estimation methodologies applicable on transaction-level system descriptions.
From a conceptual viewpoint, we could expect a possible penalty
in estimation accuracy when moving from RTL to transaction level
power estimation techniques. In fact transaction-level techniques are
applied on system prototypes at a higher abstraction level and with
less implementation details than RTL representations. As a consequence,
the run-time information achievable from a transaction-level
prototype, and used in power model application, can be less detailed
and precise. However, this possible loss of accuracy can be strongly
mitigated if we consider a transaction-level estimation technique
based on a macro-model approach [2], in which transaction-level
metrics are connected to precise power measures coming from a
low-level system implementation, such as the logic-level or the gatelevel
architecture.
The starting point for a research on transaction-level power estimation
is to fix a reference language suitable for transaction-level
modeling. In recent times, SystemC language has provided an extension
specifically dedicated to transaction-level descriptions, (SystemC/
TLM) [10], which is probably the most relevant contribution in the
formalization of a transaction-level modeling standard. As a consequence,
SystemC/TLM is the most proper platform to define methodologies
and CAD instruments for transaction-level power analysis.
SystemC language has already been at the center of some
studies on transaction-level power analysis [11–15]. However,
some of the resultant techniques [11–13] are referred to the core
capabilities of the language, without applying the specific constructs
provided by SystemC/TLM. In this way, they are precluded
from the design advantages achievable from SystemC/TLM in
terms of modeling facilities and simulation speed up. Examples
of techniques relying on SystemC/TLM constructs are reported in
[14,15]. The first contribution is a methodology based on the
classification and power characterization of the functional tasks
involved in transaction-level operations. The procedural steps are
illustrated through a case study on IBM CoreConnect architectures.
The experimental results show a good accuracy if there is a good
matching between the considered functional tasks and the transactions
generated in the run-time behavior of the system. This
technique is applicable for SystemC/TLM prototypes in which the
inter-module communications are based on the blocking transport
interface [10]. On the other hand, the approach presented in [15] is
a power state estimation technique aimed at evaluating the power
dissipation in the main operative conditions and in reference to
different system architectures. Even though the estimation results
are not very accurate, the primary intent is to realize a fast
comparison of the possible architecture alternatives. Analogously
to [14], the application of this technique is restricted to prototypes
based on the blocking transport interface.
This paper presents a transaction-level power estimation methodology
valid for SystemC/TLM descriptions and of general applicability.
In our researches, we have considered how to formalize the mapping
of functional tasks onto the basic SystemC/TLM constructs that model
transactions, without introducing restrictions related to the applied
transport interface. By following an ad-hoc macro modeling technique [2] these SystemC/TLM constructs can be properly associated to energy
estimations derived from measures on a low-level system implementation.
In this way, we can estimate the energy of the transactions
executed during a simulation session. Furthermore, we have studied
the possibility to tune the estimation accuracy on the basis of the data
transported by transactions.
In order to implement and verify the proposed approach, we
have also realized a specific CAD tool that extends the SystemC/
TLM language and is incorporated within the Power Kernel tool
(PKtool) framework [13], [16–20]. PKtool is a simulation environment
born from an academic project and dedicated to power
analysis on digital systems modeled in SystemC/Cþ þ. An open
source release of the tool we have realized is available in [16].
This paper is structured as follows. In Section 2, a preliminary
introduction on SystemC/TLM language is reported. Section 3 describes
the details of the proposed methodology in conceptual and
operative terms, while Section 4 provides the guidelines for a concrete
application on SystemC/TLM prototypes. Section 5 explains how our
methodology can be extended to cover power optimization techniques.
Finally, some experimental results are illustrated in Section 6,
considering also performance comparisons with RTL representations.
Our methodology provides estimations in terms of energy; the ratio
with simulation times allows to estimate also average power dissipations.
To avoid ambiguities, in the remainder of the paper we often use
expressions such as ‘power dissipation’ or ‘power estimation’ in
conventional way, without an explicit reference to a physical quantity.
 


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