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VL7301 Testing of VLSI Circuits – Question Bank
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.doc  1457882508-VL7301Questionbank.doc (Size: 877 KB / Downloads: 39)


UNIT – I
PART – A
1. State the need for testing. (June 2010)
2. Define Fault dominance.
3. Define Fault equivalence. (June 2010)
4. List out the different types of simulation.
5. State the two basic differences between combinational and sequential circuits. (Nov 2014)
6. How are faults modelled at Gate levels in Digital Circuits? (Nov 2010)
7. Define one pass and two pass strategy.
8. Write down the condition for detectable fault and also justify the same.
9. What are the two basic steps in Test Generation using Path sensitization method? (Nov 2014)
10. Define event driven simulation.
11. What are the types of Fault model?
12. Define Stuck-at-fault.
13. State the Lemma rule.
14. What is redundancy?
15. Define Bridging fault and mention its types.
16. What is the difference between transient and intermittent fault?
17. What are the advantages of event driven simulation over other simulation?

PART - B
1. For the circuit given below
a. Find the set of all tests that detect the fault a s-a-0.
b. Find the set of all tests that detect the fault b s-a-0.
c. Find the set of all tests that detect the multiple fault (a s-a-0, b s-a-0).

2. Explain in detail about Delay model.
3. Discuss on the various types of fault simulation techniques used in digital circuits. (Nov 2010)
4. Discuss on the faults in digital circuits and its modelling at various levels of IC diagram. (Nov 2010)
5. Show that the two faults c s-a-0 and f s-a-1are equivalent in the following circuit.


6. For the circuit given below

a. Find the set of all tests that detect the fault b s-a-1.
b. Find the set of all tests that distinguish the faults a s-a-0 and c s-a-0
c. Find the set of all tests that distinguish the multiple faults {a s-a-0, b s-a-1} and (c s-a-0, b s-a-1}.
7. Discuss on Gate level Event driven simulation.
8. Determine the output function of the circuit given below for the following faults:
a. AND bridging between inputs of gate G1.
b. The multiple faults {x3 s-a-1, x2 s-a-0}.


UNIT – II
PART – A
1. Mention any four methods used in test generation for combinational circuits?
2. Mention any two methods used in test generation for sequential circuits
3. Define homing and distinguishing tree.
4. List out the three phases of checking experiment.
5. Define Controllability and Observability.
6. Construct propagation D-cubes for two-input NOR gate.
7. Write Read-Muller expansion for three variable functions.
8. Define D frontier.
PART – B
1. Explain D algorithm with a suitable example.
2. Explain in detail about the following methods to generate test pattern of combinational circuits.
a. One-Dimensional path sensitization
b. Boolean Difference
3. Consider the logic circuit shown below; determine the set of test using partial Boolean difference associated with the path x2-l-n-p-F

4. Explain how test sequence is generated in sequential circuits using checking experiments with example.
5. Explain in detail about PODEM algorithm.
6. Write short notes on
a. Reed-Muller Expansion technique
b. Syndrome-testable design
7. Describe on Scan-path technique for testable sequential circuit design.
8. Using successor tree, determine the homing and distinguishing sequence for the state table shown below and also justify the sequence using response table.
Present State Input
x=0 x=1
A C,1 D,0
B D,0 B,1
C B,0 C,1
D C,0 A,0
9. With suitable example, explain Three-level OR-AND-OR design.
10. Explain how sequential circuits are tested using time frame expansion method.
11. Explain PODEM algorithm and using PODEM find a test vector for the fault ‘X S/O’ in the circuit shown in Figure

UNIT – III
PART – A
1. What are the problems encountered when you use Oscillators and Clocks during DFT?
2. What are the advantages of double Latch LSSD?
3. Draw L1/L2 latch and mention its significance. (Nov 2010)
4. What is controllability and observability? (Nov 2010)
5. What are the advantages of partitioning of large combinational circuit? Give example.
6. What are the advantages of using DFT approach for testing? (June 2010)
7. Give any two LSSD rules. (June 2010)
8. What are the classifications of test points?
9. Define Initialization.
10. State the need for Ad-hoc design in testing a digital circuit. (Nov 2014)
11. List out the types of generic scan based design.
12. List out the uses of scan design.

PART – B

1. List out the LSSD design rules and explain each rule.
2. Determine if the circuit shown below is a maximal test concurrency circuit, and derive a minimum verification test for this circuit.
3. What are the techniques adopted in Ad-hoc design for testability techniques? Exaplain any three techniques with an example.
4. Explain the different types of Generic scan based design.
5. Using suitable circuit diagram explain Raceless two port D flipflop as a storage cell.
6. How Ad-hoc designs are used to improve testability digital circuits? Explain with examples. (June 2010)
7. Discuss on System Level DFT techniques. (Nov 2010)
8. Explain about the following i) Classical scan based design and ii) LSSD design rule

UNIT – IV
PART – A
1. What are the different types of testing?
2. What is meant by Built-in self-test? (Nov 2014)
3. Sketch the generic form of centralized BIST architecture.
4. Differentiate between exhaustive and pseudoexhaustive testing?
5. List out the different form of segmentation.
6. What are the key elements in BIST architecture?
7. List out the several factors highlighting the choice of BIST architecture.
8. Draw the functional block diagram of TAP. (Nov 2014)
9. Define maximal test concurrency circuit.
10. Draw the circular BIST architecture. (June 2010)
11. List out the categories of test pattern generation approaches for BIST.
12. How memory is tested using March algorithm? (June 2010)
13. What are the different types of coupling faults existing in memories? (Nov 2010)
14. Draw the BILBO architecture. (Nov 2010)
15. List out the BIST architectures.
16. What do you mean by Pseudo-exhaustive test? (Nov 2014)
17. Mention the test algorithms for RAMs.
18. What are the methods to derive n input and m output combinational circuit?
19. Give the name of any two algorithms that is used for test pattern generation in Embedded RAMs. (Nov 2014)
20. List out any four advantages of circular BIST.
21. List the classification of off-line BIST Architecture.

PART – B
1. Discuss the fault models used in memories and explain how test generation is done for embedded RAM. (June 2010)
2. Discuss the test pattern generators used in BIST. (June 2010)
3. Draw the circular BIST architecture and explain how testing is done using this architecture. (Nov 2010)
4. Explain any two test algorithms used for testing memories. (Nov 2010)
5. What are the different methods available to generate pseudo exhaustive test pattern? Explain any two methods,
6. What are the faults that occur in high density memory chips? How do you overcome this?
7. Briefly discuss about the testing methodology adopted for testing embedded RAMs.
8. Explain about test generation and Built in self-test for embedded RAM.
9. With neat diagram, explain in detail about LSSD single-latch and double-latch design.
10. Discuss in detail about various DFT approaches used in testing a digital circuit. (Nov 2014)
UNIT – V
PART – A
1. What is the function of a checker in a self-checking system? (June 2010)
2. What is guided probe testing? (June 2010)
3. What is self-checking checkers? List out its advantages.
4. What is Fault dictionary? (Nov 2010)
5. What is the need for fault diagnosis? (Nov 2010)
6. What are the components in fault diagnosis? (Nov 2014)
7. What do you mean by dynamic diagnosis? (Nov 2014)

PART – B

1. Explain how diagnosis is done by UUT reduction. (June 2010)
2. Describe the functioning of totally self-checking m/n code checkers and self-checking Berger codes checkers. (June 2010)
3. Explain the functionality of checkers in self checking design with examples (Nov 2010)
4. Discuss on fault diagnosis for combination circuits. (Nov 2010)
5. Briefly explain how guided probe is used for testing the internal signals of UUT.
6. Explain in detail about the methods adopted for fault diagnosis in combinational circuit.(Nov 2104)
7. Discuss in detail how self checking method is adopted to test a circuit to diagnosis the fault. (Nov 2014)
 


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